Adaptive Ternary A/D Converter for Use in an Ultra-Wideband Communication System

ABSTRACT

In an ultra-wideband communication system, a 1-trit ternary analog-to-digital converter (“ADC”) having dynamic threshold adaption and providing an output in ternary form [+1, 0, −1]. The ternary ADC includes a pair of 1-bit binary ADCs, one being configured in a non-inverting form, and one being configured in an inverting form. Each binary ADC includes an feedback network mechanism, thereby allowing for simultaneous and independent adaptation of the pair of thresholds, compensating for the effects of any DC offset that may be present. The use of a trit-based ternary encoding scheme improves system entropy.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of application Ser. No. 13/033,098,filed 23 Feb. 2011 (“Parent Application”). This application claimspriority to U.S. Provisional Patent Application Ser. No. 61/316,299(“Parent Provisional”), filed 22 Mar. 2010. The foregoing ParentApplication and Parent Provisional are hereby incorporated by referencein their entirety as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to ultra-wideband communicationsystems, and, in particular, to a ternary analog-to-digital converterfor use in an ultra-wideband communication system.

2. Description of the Related Art

In general, in the descriptions that follow, we will italicize the firstoccurrence of each special term of art, which should be familiar tothose skilled in the art of ultra-wideband (“UWB”) communicationsystems. In addition, when we first introduce a term that we believe tobe new or that we will use in a context that we believe to be new, wewill bold the term and provide the definition that we intend to apply tothat term. In addition, throughout this description, we will sometimesuse the terms assert and negate when referring to the rendering of asignal, signal flag, status bit, or similar apparatus into its logicallytrue or logically false state, respectively, and the term toggle toindicate the logical inversion of a signal from one logical state to theother. Alternatively, we may refer to the mutually exclusive booleanstates as logic_0 and logic_1. Of course, as is well know, consistentsystem operation can be obtained by reversing the logic sense of allsuch signals, such that signals described herein as logically truebecome logically false and vice versa. Furthermore, it is of norelevance in such systems which specific voltage levels are selected torepresent each of the logic states.

Generally, in an ultra-wideband (“UWB”) communication system, a seriesof special processing steps are performed by a UWB transmitter toprepare payload data for transmission via a packet-based UWB channel.Upon reception, a corresponding series of reversing steps are performedby a UWB receiver to recover the data payload. Details of both series ofprocessing steps are fully described in IEEE Standards 802.15.4(“802.15.4”) and 802.15.4a (“802.15.4a”), copies of which are submittedherewith and which are expressly incorporated herein in their entiretyby reference. As is known, these Standards describe required functionsof both the transmit and receive portions of the system, but specificimplementation details only of the transmit portion of the system,leaving to implementers the choice of how to implement the receiveportion.

One of us, Michael McLaughlin, has developed certain improvements foruse in UWB communication systems, which improvements are fully describedin the following pending applications or issued patents, all of whichare expressly incorporated herein in their entirety:

“A Method and Apparatus for Generating Codewords”, application Ser. No.11/309,221, filed 13 Jul. 2006;

“A Method and Apparatus for Generating Codewords”, application Ser. No.11/309,222, filed 13 Jul. 2006, now abandoned;

“A Method and Apparatus for Transmitting and Receiving ConvolutionallyCoded Data”, U.S. Pat. No. 7,636,397, issued 22 Dec. 2009; and

“A Method and Apparatus for Transmitting and Receiving ConvolutionallyCoded Data”, application Ser. No. 12/590,124, filed 3 Nov. 2009.

Some of us have participated in the development of certain improvementsin a receiver for use in UWB communication systems, which improvementsare fully described in the following pending application, which isexpressly incorporated herein in its entirety:

“A Receiver for Use in an Ultra-Wideband Communication System”,application Ser. No. 12/885,517 (Attorney Docket # JDW005), filed 19Sep. 2010 (“Related Application”).

A problem of particular note in these spread-spectrum systems is anatural tension between simplicity, low power, and performance. Withinthe context of a spread-spectrum system, support for the above mentioned802.15.4a standard is premised upon the ability to quickly andaccurately convert the transmitted analog signal to a correspondingdigital equivalent for processing, and at the same time minimizing theoverall size and power of the associated circuitry. This desire forreduced area and power would naturally lead to quantizing as coarsely asthe desired performance will permit. While it has been proposed toimplement the front-end of a spread-spectrum receiver using a fast,1-bit analog-to-data converter (“ADC”) to reduce the size (in terms oftransistor count) of the convolution logic in both the channel impulseresponse (“CIR”) estimator and the channel matched filter (“CMF”), suchimplementations are known to be particularly sensitive tocontinuous-wave (“CW”) interference. This CW interference can besubstantially rejected using a full 2-bit, sign+magnitude implementationsuch as that described by F. Amoroso in “Adaptive A/D Converter toSuppress CW Interference in DSPN Spread-Spectrum Communications”, IEEETrans. on Communications, vol. COM-31, No. 10, October 1983, pp.1117-1123 (“Amoroso83”), a copy of which is submitted herewith and whichis expressly incorporated herein in its entirety by reference.

We have noted that, in a system adapted to quantize in units of binarydigits or bits, such as that described in Amoroso83, having dualrepresentations of the O-state, i.e., [−0, +0], tends to increase systementropy, resulting in less-than-optimal circuit/power efficiency. Onepossible solution would be to implement a system adapted to quantize inunits of ternary digits or trits, such as that used in a pair of obscurecomputers built in the Soviet Union many years ago. See, “A Visit toComputation Centers in the Soviet Union,” Comm. of the ACM, 1959, pp.8-20; and “Soviet Computer Technology—1959”, Comm. of the ACM, 1960, pp.131-166; copies of which are submitted herewith and which are expresslyincorporated herein in their entirety by reference. Unfortunately, today(as was the case in these old machines), the available circuittechnology is unable efficiently to represent and manipulate trits perse.

We submit that what is needed is an improved method and apparatus foruse in the receiver of a UWB communication system for performing theanalog-to-digital conversion. In particular, we submit that such amethod and apparatus should provide performance generally comparable tothe best prior art techniques while requiring less circuitry andconsuming less power than known implementations of such prior arttechniques.

BRIEF SUMMARY OF THE INVENTION

In accordance with the preferred embodiment of our invention, we providean analog-to-digital converter (ADC) comprising a first comparator, afirst feedback network, a second comparator, and a second feedbacknetwork. The first comparator is adapted to receive an analog signal andto receive a first feedback voltage. The first comparator compares theanalog signal and the first feedback voltage, and generates a logic_1value if the analog signal is greater than the first feedback signal.Conversely, the first comparator will generate a logic_0 value if theanalog signal is less than the first feedback voltage. The firstfeedback network is adapted to develop the first feedback voltage as afunction of an average of the values output by the first comparator. Thesecond comparator is adapted to receive an analog signal and to receivea second feedback voltage. The second comparator compares the analogsignal and the second feedback voltage, and generates a logic_1 value ifthe analog signal is less than the second feedback signal. Conversely,the second comparator will generate a logic_0 value is the analog signalis greater than the second feedback voltage. The second feedback networkis adapted to develop the second feedback voltage as a function of anaverage of the values output by the second comparator.

In accordance with another preferred embodiment of our invention, weprovide a method of analog to digital conversion. The method comprisesthe steps of receiving an analog signal, receiving a first feedbackvoltage, comparing the analog signal to the first feedback voltage, andresponding by providing a first output. This first output will have alogic_1 value if the analog signal is greater than the first feedbackvoltage, and it will have a logc_0 value if the analog signal is lessthan the first feedback voltage. The method further comprises the stepof developing the first feedback voltage as a function of an averagenumber of the values of the first output. The method further comprisesthe steps of receiving a second feedback voltage, comparing the analogsignal to the second feedback voltage, and responding by providing asecond output. This second output will have a logic_1 value if theanalog signal is less than the second feedback voltage, and it will havea logc_0 value if the analog signal is greater than the second feedbackvoltage. The method further comprises the step of developing the secondfeedback voltage as a function of an average of the values of the secondoutput.

In accordance with another preferred embodiment of our invention, weprovide a method of analog to digital conversion. The method comprisesthe steps of receiving by a first comparator an analog signal, receivingby the first comparator a first feedback voltage, comparing by the firstcomparator the analog signal to the first feedback voltage, andresponding by providing a logic_1 value if the analog signal is greaterthan the first feedback voltage and a logic_0 value if the analog signalis less than the first feedback voltage. The method further comprisesthe step of developing by the first feedback network the first feedbackvoltage as a function of an average number of the values output by thefirst comparator. The method further comprises the steps of receiving bya second comparator an analog signal, receiving by the second comparatora second feedback voltage, comparing by the second comparator the analogsignal to the second feedback voltage, and responding by providing alogic_1 value if the analog signal is less than the second feedbackvoltage and a logic_0 value if the analog signal is greater than thesecond feedback voltage. The method further comprises the step ofdeveloping by the second feedback network the second feedback voltage asa function of an average number of the values output by the secondcomparator.

In accordance with another preferred embodiment of our invention, weprovide an analog-to-digital converter (ADC) comprising a first binaryADC adapted to receive an analog input and to produce a first binaryvalue as a function of the input and a positive analog feedback signal.The ADC further comprises a second binary ADC adapted to receive theanalog input and to produce a second binary value as a function of theinput and a negative analog feedback signal. The first and second ADCeach comprise a comparator which is adapted to provide the respectivebinary value as a function of the analog signal and the respectivefeedback signal, and a feedback network adapted to provide therespective feedback signal as a function of an average of the respectivebinary values.

In accordance with another preferred embodiment of our invention, weprovide a method of analog-to-digital conversion comprising the stepsof: developing a first binary value of an analog input signal byperforming a 1-bit analog to digital conversion in a non-inverting form;and, developing a second binary value of the analog input signal byperforming a 1-bit analog to digital conversion in an inverting form.Each of the developing steps further comprises the steps of: developinga respective binary value by comparing the analog signal and arespective analog feedback voltage, the binary value having a firstlogic value if the analog signal is greater than the respective feedbackvoltage, and a second logic value if the analog signal is less than therespective feedback voltage; developing an average of the binary values;developing a smoothed average of the average; and, developing therespective analog feedback voltage by performing a digital to analogconversion of the smoothed average.

We submit that each of the embodiments provides an improved method orapparatus for use in the receiver of a UWB communication system forperforming the analog-to-digital conversion. In particular, we submitthat each of our embodiments provides performance generally comparableto the best prior art techniques while requiring less circuitry andconsuming less power than known implementations of such prior arttechniques.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Our invention may be more fully understood by a description of certainpreferred embodiments in conjunction with the attached drawings inwhich:

FIG. 1 illustrates, in block diagram form, a trit-based ADC constructedin accordance with a preferred embodiment of our invention;

FIG. 2 illustrates, in block diagram form, the general form of each ofthe 1-bit ADCs illustrated in FIG. 1;

FIG. 3 illustrates, in block diagram form, the general form of thenegative feedback network illustrated in FIG. 2;

FIG. 4 illustrates, in block diagram form, the general form of thepositive feedback network illustrated in FIG. 2;

FIG. 5 illustrates, in block diagram form, the general form of a lowpass filter suitable for use in the feedback network illustrated in FIG.3;

FIG. 6 illustrates the frequency response of an exemplary embodiment ofthe low pass filter illustrated in FIG. 5; and

FIG. 7 illustrates, by way of example, the operation of the ADC of FIG.1 as it adapts the positive and negative feedbacks to compensate for a50 mV DC offset.

In the drawings, similar elements will be similarly numbered wheneverpossible. However, this practice is simply for convenience of referenceand to avoid unnecessary proliferation of numbers, and is not intendedto imply or suggest that our invention requires identity in eitherfunction or structure in the several embodiments.

DETAILED DESCRIPTION OF THE INVENTION

In accordance with the preferred embodiment of our invention illustratedin FIG. 1, our trit-based analog-to-digital converter (“ADC”) 10 (note:hereinafter, we will underline the reference numeral of an element toemphasize that it operates in a trit mode) includes a non-inverting1-bit ADC 12A, an inverting 1-bit ADC 12B, and a binary-to-ternaryrecoder 14. In general, the analog input signal 16 is applied toselected inputs 16A/B of ADCs 12A/B, and, in response, each provides arespective binary output, 18A/B. Recoder 14 is adapted to receive thebinary outputs 18A/B generated by ADCs 12A/B, and to provide a tritoutput 20 in ternary form, i.e., [−1, 0, +1].

In the context of our invention, our ADC 10 can be distinguished from aconventional sign+magnitude implementation such as that described inAmoroso83, cited above. Consider the strategy for A/D conversion shownin FIG. 5 of Amoroso83; and, note, especially, that there are threeseparate and distinct switching thresholds: (i) a sign threshold [T₀];(ii) a positive magnitude threshold [T₀+Δ]; and (iii) a negativemagnitude threshold [T₀−Δ]. (See, also, Amoroso83, p. 1119, lines21-24.) We have discovered that adapting our ADC 10 to use ONLY thepositive and negative thresholds results in only a very small loss inresolution. Accordingly, in our preferred embodiment, ADC 10 does notimplement a separate and distinct sign threshold [T₀], therebysimplifying the circuit while simultaneously improving the conversiontime of the ADC 10 and most importantly, considerably simplifying thedigital processing required after the ADC. In contrast to a conventionalsign+magnitude implementation, our trit-based ADC 10 can be readilyadapted to operate either at a higher sample rate (improved performancebut with more power) or at an equivalent sample rate (substantiallyequivalent performance but with less power).

As will be apparent, during normal operation, the ADCs 12A/B may developfour different output combinations; each is recoded by recoder 14 intothree distinct trit values as indicated in the following Table 1:

TABLE 1 Recoding of comparator outputs to trit values. Positive NegativeComparator Comparator Output Output Trit Value 0 0 0 0 1 −1 1 0 +1 1 1 0

We have defined this recoding such that normal zero crossings of theanalog input signal 16, i.e., when both ADCs 12A/B simultaneously outputa logic_0, are recoded to the trit_0 value. In certain cases, such aswhen the analog input 16 is very near zero and the ADCs 12A/B are notelectrically identical, both ADCs 12A/B may simultaneously outputlogic_(—)1 values. Since this situation will, in general occurrelatively rarely, we prefer to recode this case to the trit_0 value.

As shown in FIG. 2, each of our ADCs 12 x comprises a high-gainoperational amplifier 22 x (referred to hereinafter as a comparator),and a feedback network 24 x. In accordance with our invention, feedbacknetwork 24 x is adapted dynamically to adjust the switching threshold ofthe comparator 22 x to compensate for any DC offset that may be presentin the analog input 16 x.

In ADC 12A, the feedback network 24[A] is connected to the invertinginput of comparator 22[A] so as to provide a negative feedback voltageas a function of the output, averaged over time, of comparator 22[A]. Inoperation, comparator 22[A] performs an analog comparison of analoginput 16A and the negative feedback voltage; and provides a logic_1value when analog input 16A is higher than the negative feedbackvoltage, and a logic_0 value when analog input 16A is lower than thenegative feedback voltage.

In ADC 12B, the feedback network 24[B] is connected to the non-invertinginput of comparator 22[B] so as to provide a positive feedback voltageas a function of the output, averaged over time, of comparator 22[B]. Inoperation, comparator 22[B] performs an analog comparison of analoginput 16B and the positive feedback voltage; and provides a logic_1value when analog input 16B is lower than the positive feedback voltage,and a logic_0 value when analog input 16B is higher than the positivefeedback voltage.

In accordance with our invention, a suitable feedback network 24 x,illustrated in FIG. 3, comprises an averager 26 x, a low pass filter 28x, and a digital-to-analog converter (“DAC”) 30 x. In accordance withour invention, averager 26A/B is adapted to monitor the respectiveoutput 18A/B, and to determine the average number of non-zero samplesover a predetermined averaging interval. In general, the averaginginterval should encompass a reasonably large number of samples.Depending on the desired operating characteristics of ADC 10, averager26A/B may be adapted to develop the average periodically, i.e., onceeach averaging interval, For example, in one periodic embodiment,averager 26A/B may be adapted to sum 1024 samples taken over anaveraging interval of, say, 1 microsecond, then to divide that sum bythe total number of samples taken during that averaging interval (i.e.,1024 in this example); the resultant quotient, comprising a staticsnapshot of the moving average, would be provided for the duration ofthe next subsequent averaging interval. Alternatively, in one continuousembodiment, averager 26A/B may be adapted to store, e.g., in a 1-bitwide digital delay line of length 1024, only the most recent set of 1024samples taken during the same 1 microsecond averaging interval; inresponse to each new sample, the storage is cycled so as tosimultaneously store the new sample while discarding the oldest sample.In this embodiment, averager 26A/B may update the moving average everysample time, thereby providing a more dynamic moving average. Dependingon power and performance considerations, as deemed appropriate, themoving average may be updated less often than every sample interval butmore often than once each averaging interval.

In accordance with our invention, low pass filter 28A/B is adapted toreceive the averages developed by averager 26A/B, and to develop arespective feedback voltage as a function of a smoothed average of aplurality of the most-recently received averages. As illustratedgenerally in FIG. 5, a suitable low pass filter 28A/B may implement aninfinite impulse response (“IIR”) transfer function, of the form:

y _(n) =αβx _(n)+(1−α)y _(n-1)

wherein:

-   -   α determines how fast the filter adapts; and    -   β controls the proportion of 1's values that will appear in the        output.

In one embodiment, the frequency response of which is illustrated inFIG. 6, the value for the α term is set at 1/16, and the value for the βterm is set to 4. FIG. 7 shows how the comparator thresholds vary withtime when the input is Gaussian noise with a 50 mV DC offset and astandard deviation of 145 mV.

In alternate embodiments, coding of trit could be performed in a varietyof ways. For example, in one embodiment, the coding of trit could be asa 2's complement value. As a different example, in a differentembodiment, the coding of the trit could be as a sign value and amagnitude value. The actual values assigned in the differing examplesrecited previously can also be encoded a variety of ways. For example,−1 could be represented as 11, 10, 01 or 00. Any representation would besufficient as long as it can be distinguished from a 0 value and +1value in the system.

In alternate embodiments, the low pass filter may be implemented usingdiffering forms of the IIR transfer function chosen from the many formsavailable in this field of art. Alternatively, the low pass filter maybe implemented using a finite impulse response (“FIR”) transfer functionchosen from the many forms available in this field of art.

In our Related Application, we have disclosed an ultra-wideband receiverspecially adapted to implement a trit-based ADC constructed inaccordance with our invention. As noted therein, use of our ADC in sucha system provides distinct advantages over other known ADC technologies.

Thus it is apparent that we have provided a trit-based method andapparatus for analog to digital conversion, the performance of which isgenerally comparable to the best prior art binary techniques whilerequiring less circuitry and consuming less power that knownimplementations of such prior art techniques. Those skilled in the artwill recognize that modifications and variations can be made withoutdeparting from the spirit of our invention. For example, thefunctionality of the feedback network 24 x may be implemented insoftware or hardware or a combination thereof. Therefore, we intend thatour invention encompass all such variations and modifications as fallwithin the scope of the appended claims.

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 29. Ananalog-to-digital converter (ADC) comprising: a first binary ADC adaptedto receive an analog input and to produce a first binary value as afunction of said input and a positive analog feedback signal; and asecond binary ADC adapted to receive said analog input and to produce asecond binary value as a function of said input and a negative analogfeedback signal; wherein each of said first and second ADCs comprises: acomparator adapted to provide said respective binary value as a functionof said analog signal and said respective feedback signal; and afeedback network adapted to provide said respective feedback signal as afunction of an average of said respective binary values.
 30. The ADC ofclaim 29 further comprising a recoder circuit adapted to provide adigital output in ternary form as a function of said first and secondbinary values.
 31. The ADC of claim 30 wherein said feedback network isfurther characterized as comprising: an averaging circuit adapted to:sample said binary value during each of a plurality of sample intervals;and provide an average value as a function of the average number ofnon-zero values sampled during an averaging interval comprising apredetermined number of sample intervals; a low pass filter adapted toreceive each of said average values and to provide a smoothed average ofsaid received average values; and a digital-to-analog converter (DAC)adapted to receive said smoothed average and to convert said smoothedaverage to said feedback signal.
 32. The ADC of claim 31 wherein asampling frequency of said sample intervals is substantially lower thanan operating frequency of said analog input.
 33. The ADC of claim 32wherein said sample interval is substantially smaller than the averaginginterval.
 34. The ADC of claim 32 wherein said averaging circuitprovides said average value once each averaging interval.
 35. The ADC ofclaim 32 wherein said averaging circuit provides said average value onceeach sampling interval.
 36. The ADC of claim 32 wherein said low passfilter is further characterized as an IIR low pass filter. 37.(canceled)
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 45. An analog-to-digitalconverter (ADC) comprising: a first binary ADC adapted to receive ananalog input and to produce a first binary value as a function of saidinput and a positive analog feedback signal; and a second binary ADCadapted to receive said analog input and to produce a second binaryvalue as a function of said input and a negative analog feedback signal;and a recoder circuit adapted to provide a digital output in ternaryform as a function of said first and second binary values; wherein eachof said first and second ADCs comprises: a comparator adapted to providesaid respective binary value as a function of said analog signal andsaid respective feedback signal; and a feedback network adapted toprovide said respective feedback signal as a function of an average ofsaid respective binary values.
 46. The ADC of claim 45 wherein saidfeedback network is further characterized as comprising: an averagingcircuit adapted to: sample said binary value during each of a pluralityof sample intervals; and provide an average value as a function of theaverage number of non-zero values sampled during an averaging intervalcomprising a predetermined number of sample intervals; a low pass filteradapted to receive each of said average values and to provide a smoothedaverage of said received average values; and a digital-to-analogconverter (DAC) adapted to receive said smoothed average and to convertsaid smoothed average to said feedback signal.
 47. The ADC of claim 46wherein a sampling frequency of said sample intervals is substantiallylower than an operating frequency of said analog input.
 48. The ADC ofclaim 47 wherein said sample interval is substantially smaller than theaveraging interval.
 49. The ADC of claim 47 wherein said averagingcircuit provides said average value once each averaging interval. 50.The ADC of claim 47 wherein said averaging circuit provides said averagevalue once each sampling interval.
 51. The ADC of claim 47 wherein saidlow pass filter is further characterized as an IIR low pass filter.